(a) Field of the Invention
The present invention relates to a MOS transistor and a method for fabricating a semiconductor device, and in particular, to a method for fabricating a MOS transistor.
(b) Description of the Related Art
The MOS transistor, which is a field effect transistor (FET), has source and drain regions formed in a semiconductor substrate and a gate oxide layer and a gate formed over a channel generally defined by the source/drain regions. In this MOS transistor structure, metal wires are connected to the source, the drain, and the gate electrodes such that the transistor operates by applying electric signals thereto. A method for fabricating the above structured MOS transistor will be explained hereinbelow.
Firstly, a lightly doped drain (LDD) is formed by depositing a gate oxide layer and a polysilicon layer sequentially on the surface of the active region of the silicon wafer, and injecting or implanting (hereinafter, “injecting”) a P-type or N-type dopant into the silicon wafer of the device region using a gate made from the polysilicon as a mask, and forming spacers on both sides of the polysilicon gate. Next, the source/drain regions are formed by injecting a high concentration of dopant ions of a type identical with that of the LDD into the device region of the silicon wafer.
The gate CD (critical dimension) of MOS transistors fabricated in the above-explained manner has recently tended to decrease in order to increase the density and/or integrality of the devices. However, the decrease of the gate CD requires shortening a length of the channel. In particular, the channel length has become much shorter between the source and drain regions in which the impurity ions are injected, due to diffusion of the impurity ions. If the channel length is excessively shortened as such, a leakage current is generated even with the LDD structure, adjustment of an off-current becomes difficult with direct current, and a breakdown occurs due to the narrowed depletion region between the source and drain. A leakage current is also generated when the carriers move from the source to the drain through the channel at a voltage lower than an operational voltage.
Accordingly, needs for a MOS transistor having a novel structure which is advantageous for miniaturizing the device while at the same time reducing leakage current, and a method for fabricating such a transistor have been felt.
U.S. Pat. No. 5,627,097 discloses a technique for forming the channel region using an epitaxial layer, and U.S. Pat. No. 5,872,039 discloses a technique for reducing the diffusion regions of the source/drain terminals.